1. Field of the Invention
The present invention relates to an information processing system, or more particularly, to an information processing system in which memory devices and copies of tags are accessed in response to access requests issued from a plurality of processing units.
2. Description of the Related Art
In recent years, an art for enabling an information processing system to operate at a high speed using as small a number of logic devices, and as little wiring, as possible has been demanded in conformity with the trend toward a higher density of components and a higher operating speed.
A control sequence for controlling access to memories or memory access in a known information processing system will be described.
The known information processing system comprises a plurality of processing units, memory devices, tag RAMs, and a system controller. Each processing unit has a cache memory and a tag RAM. In the tag RAMs, copies of tags of all the processing units are stored.
When each processing unit accesses a memory, first, the processing unit attempts to index and update the contents of its own tag. If desired data is stored in its own cache memory, the processing unit accesses the cache memory. If the desired data is not stored in its own cache memory, the processing unit issues a memory access request to the system controller. The system controller indexes and updates the copies of tags stored in the tag RAM. If it is found as a result of indexing that the desired data is not stored in any other processing unit, access to memory, or a memory access, is needed. The memory device is therefore activated.
In the known information processing system, as the number of processing units increases, the competition among the processing units for a memory access control unit becomes fierce. Consequently, the efficiency of memory access deteriorates.